Put your Flip Flops on, let's go for a deep dive.
The 74HC74 (or 74LS74 or 74HCT 74 etc.) is a commonly used part in my designs and many others.
I thought it would be interesting to have a bit of a run through some of the many and varied uses of such a useful chip.
It is a dual D-Type Flip Flop. With two halves, each of which can be
- A clocked latch
- A set / reset latch
- A flip / flip
And various combinations of the above.
It is the combinations which make it such a simple and yet powerful building block.
It was one of these combinations which sparked this piece. I had a great idea at 3AM one morning, but wasn't sure if it would work, and it required a bit of thinking through and tweaking the design to get there.
I thought it might be interesting to go through some of the many and varied uses of the 74HC74 in my designs.
So what is it?
The 7400 series was introduced in the mix 1960s, with the 74LS in the early 1970s and 74HC in the early 1980s.
It blows my mind in a world where technology changes so quickly that essentially the same parts have been in production for nearly 70 years. (yes, I know those are 175s, and yes I know HC isn't the same as LS, that was just the ones I happened to have a picture of)
This 74LS74 dated 1977 is in my Commodore PET 2001.
That's a Motorola version, this was the earliest Texas Instruments one I could find on any of my boards, first week 1980.
Here is one from 2020 (if I read the date code correctly) on a Minstrel 2.
The pinout
The first flip flop uses pins 1-6, the second pins 8-13, with the power on the corners as was usual for 74 series TTL chips (apart from a few oddballs, including the early 5474)
My PCB software lets my draw my own symbols, so these are the ones I use for the 74. I add the symbol to the side of the clock to remind me it operates on the rising edge.
Each half has 4 inputs and 2 outputs, for the moment, lets look at just three of them.
Clock
The clock input is an edge triggered input, things happen on the positive rising edge of the clock signal. Most of these chips seem to be clocked on the positive rising edge.
Data
When that edge happens, it samples the D or data input and copies it to the Q output.
Simple as that.
Q
Q only changes at the point the clock input changes from 0 to 1 (or a few tens of nanoseconds after).
This is useful for things like output ports on 8-bit microprocessor systems. These usually have a timing diagram something like this.
The address and function signals (read / write, memory or IO, etc.) are set usually on one part of the processor clock cycle (not to be confused with the clock on the 74). The data is then setup in the next part, although these are only valid for the later parts of the cycle, specifically at the point where the CPU clock changes.
The decoding logic for an IO port is usually setup so the port is active when the address is matched, so will go low towards the end of the first half of the CPU clock cycle, depending on how long it takes the propagate through the decoding logic.
Most of these circuits do not reference the processor clock itself, but are based on the address changing at the start of the next processor clock cycle. As soon as the address changes, the decoding logic will cause the clock pin of the latch to go back high, and at that point, the 74 will sample the databus and copy that level on the D pin to the output Q pin.
An example of this is the save output on the Minstrel 4th. This latches the value on the D3 bit of the databus when port $FE is written to. The Q output is used to drive the microphone input of the cassette recorder.
The clocked latch can also be useful for cleaning up signals, for example the video output on the Mini PETs and Minstrels and similar computers.
These have a video output which is a combination of the output of a shift register and a separate invert signal. These allow you to get twice as many characters by creating inverted versions of the ones you already have without having to store those in ROM (or RAM).
A problem seen on the output of the ZX80 and PET 2001 on modern monitors are shadow lines at the edge of some characters, caused by the invert signal changing at a slight different time to the character data. So for a brief moment, the invert signal is still set for the previous character, but the shift register output has changed to the next character.
The flip flop can be used here to use the 6.5MHz clock edges to sample the video data signal once per character, so the output can only change once per pixel, so you get a nice neat output with no glitches.
For the PET 2001 version, I fixed that with a single gate 74 surface mount chip mounted in a board which plugs into the socket of the 74LS08 it was driving. (OK, it's called a 74LCV1G175, but it operates just like a single 74 gate)
Frequency divider
Another common use for a flip flop is as a frequency divider. Here we need to bring in another pin
/Q or Q bar
There isn't a neat "Q with a line over it" symbol I can put in the text, so I use /Q. This is simply the inverted version of Q, and is set at the same time, a complimentary pair.
If you wire the /Q output to the D input, then on each rising edge of the clock, Q will be set to the value of the previous /Q output, which is the inverse of the previous value of the Q output, so it toggles.
This can be used to generate exactly half the frequency of the clock input, here generating 3.25MHz from a 6.5MHz input.
It is also a very clean 50:50 mark:space square wave, even if the input is very asymmetric, as the output is toggling on the rising edge, so does not care when the falling edge occurs.
The same sort of thing can also be used for a toggle function. Press a button to turn something on, press it again to turn it off.
The clock in this case is a debounced signal from a push switch.
Here pressing it once sets the /Normal output high and /Turbo low, press again and they change, /Turbo goes low and /Normal goes high and so on.
This circuit also uses the two other pins.
/CLR and /PRE
The remaining two inputs are clear and preset. Unlike the clock, these are level triggered. They normally sit at logic 1, and are active when the input is logic 0.
/CLR or clear is used to clear the output of the flip flop, so any time that pin is 0, the Q output will be fixed at 0, and /Q at 1, no matter what the clock and data inputs are doing, and will stay low until the next clock pulse (or /PRE goes low)
/PRE or preset works in the same way, but presets the Q output to a 1 and /Q to a 0, and again those will stay like that all the time /PRE is low.
In the above circuit, they are used so the microcontroller can force the flip flop into one mode or the other.
It is undefined what happens if both /CLR and /PRE are low, don't do that, it may cause the universe to implode.
/CLR is quite useful to wire to the system /RESET, so that the flip flop will always start in a known state.
For example, the mic output on the Minstrel 4th could have used /CLR to force the output low after reset, but the original Jupiter Ace version didn't, so I didn't.
Shift Register
Another thing you can use a 74 for is to create a shift register. Here in the Minstrel 3 video circuit, I only needed a couple of stages, but by tying the clock inputs together and chaining Q (or /Q) to the next D, you can create a shift register which propagates a signal down the line on each clock pulse.
That is used to generate the back porch signal for the video on the Minstrel 3, driving the /CLR input as sown above to force the video output to be low for the screen borders.
The Minstrel 2 version is a bit more analogue.
The CLR input on the flip flop is driven from an RC circuit which extends the sync pulse to create a back porch for the video signal to set the black level before the white borders start.
That circuit also contains an unusual use of the 74. I needed to buffer the sync signal, but I did not have any spare gates, only half of a 74 flip flop.
I had Sync and /Sync signals, so I was able to use the 74 to recreate a version of Sync by driving the /CLR and /PRE inputs.
That was one of those times where I had to work it through all the possibilities to see if it was OK, as I had not seen it done before.
I've had a great idea....
That brings me to the idea I had a few days ago.
The Minstrel 4th can run at 3.25MHz or 6.5MHz, and this is currently selected by a pair of jumpers.
This isn't an ideal solution as I am sure someone will have tried fitting both jumpers to see if they get 9.75MHz (you don't).
The 6.5MHz used for the video circuitry is buffered by a spare 74HC86 gate and then divided down to get the 3.25MHz clock.
On the Minstrel 4D, there was quite a complicated circuit to select Trubo™ mode (on the first prototype, I managed to spell Turbo wrong, so I still call it Trubo mode).
Here the buffered clock is divided down, and the other half of the flip flop selects which clock is passed through to the output.
The OR gates here only pass through the clock when the control input is low. When /Normal or /Turbo are high, the output of their respective OR gates is always logic 1.
(There, fixed, I don't think anyone noticed)
There isn't space for all of the turbo button circuitry on the Minstrel 4th, so I was trying to think of a way of doing that with a single jumper, but without adding any parts, a 74HC257 would have done the job, but I don't want to add a whole extra chip just for that, likewise the OR / AND mixer circuit above.
I wondered if I could make the half 74HC74 that I had into some sort of configurable divider, to produce 6.5MHz or 3.25MHz.
As it currently works, on every rising edge of the 6.5MHz clock, the /Q output is copied to the Q output, so toggling it.
This gives an output which is half the frequency of the input, so we get the 3.25MHz output.
I was wondering if I could use the /CLR input to set Q low half way though the cycle and then it would always be set high again at the start of the next cycle, maintaining the 6.5MHz output.
I would use a jumper to select if /CLR should be high (for 3.25MHz) or be a short pulse on the falling edge of the 6.5MHz clock (for 6.5MHz).
My first attempt used an RC circuit.
I tried lots of values for the R and C, but I couldn't quite get the short pulse I wanted, although it did appear to work.
I wasn't happy that would be reliable, I need the /CLR signal to be safely high before CLK changes. If the /CLR signal does not rise before the CLK, then it will ignore the clock signal and the output will stay low. At half time, /CLR will force the low output to continue to be low and so on, not changing.
After some pondering, I came up with a plan B, which is to use the spare XOR gate to delay the 6.5MHz clock. The propagation delay of a 74HC86 is 10-20ns, which doesn't sound much of a delay, but consider the period of the 6.5MHz clock is only about 150ns.
The logic analyser is only measuring to 5ns, so that is only two samples.
But that is enough to make it work.
The delayed clock pulse means /CLR will not be active when the Clock rises, so it will always clock in high and at (about) half time, will be forced low.
That allows the single jumper to select 3.25MHz or 6.5MHz.
That all seems to be working nicely, so I will add that to the next revision of the board.
Other notable mentions
I should also give a mention to some of the similar chips, the 175 is a quad version which has a common clock and clear (/MR, master reset), but still has Q and /Q outputs.
The 174 is a hex version, again with common clock and clear, but does not have the /Q outputs
The 273 is an octal version.
The 374 is similar but has an output enable in place of the clear.
And finally, the 574 which is the same as the 374 but with the pins arranged in a more pleasing order.
Conclusion
All in all, a very useful chip that can be used in all sorts of ways. Have I missed out any other ways you can use a 74?
This was a bit out of the ordinary, but I hope you found it interesting.
Would you like to see more like that, following some discussions on the discord, a post on the 555 timer might be interesting?
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