Sunday, 16 February 2020

How banked ROM cartridges work

Following on from last week's blog post on the new Marina 64 banked ROM cartridge for the Commodore 64, I thought I would answer a few of the questions that post raised by going into a bit more detail.
The Commodore 64 has a processor with a 64K address space, and has 64K of RAM installed, so any ROMs need to be switched in and out of blocks of addresses within that space. There are various combinations available which swap in the system ROMs and the two 8K regions on the cartridge slot.
This is all controlled by the PLA chip, which is why you get big problems when they fail. (see a previous blog post on Commodore 64 cartridges for more information on the different modes)
As designed, a Commodore 64 cartridge would contain one or two 8K ROM chips, in various combinations, so you could have up to 16K of ROM code for your game or utility. There are two chip select lines ROM_L and ROM_H which are used to activate the ROM chips as required.
What happens if you want more? Well, in the case of the Magic Desk 1 cartridge, they needed 32K, so the code would need to be on four 8K ROM chips, but the cartridge could only be 8K or 16K? I don't know exactly what happened, but my theory is they decided they could use a single 8K ROM cartridge with one of the ROM chips in, and the other three ROM chips in a little tray by the side. Each cartridge would be supplied with a robot arm and whenever they wanted something on one of the other ROM chips, the robot arm would unplug the current ROM chip and plug in one of the others.
Due to practical issues of size and cost and sanity, they had to do that electronically. What they did was build the cartridge as if it was a single 8K ROM cartridge, so on boot a single 8K ROM is selected and works as if it were a normal cartridge. There are some IO ranges on the cartridge port, and they used one of these to add a register which latched in the address of the ROM that was required, and next time the 8K ROM range was accessed, the appropriate ROM chip would respond. No robot arms were required. The robot arms unions were furious.
The 74LS139 is a dual 2 to 4 line decoder, in each half, one of four outputs goes low based on a two bit address on the input. Here, the left hand half of the 74LS139 is used to generate the clock pulse for the data latch. This is triggered on the high going edge, so the output goes low when the clock is high, I/O 1 region is low and write is low, so the first part of the write cycle. Whilst the clock is high, the databus is being prepared with the data to be written, and when the clock goes low, it should be ready, so is latched into the 74LS175. (note on the only schematic I have found, this is incorrectly shown as connected to pin 12 of the 139, but I believe this to be a mistake as it would latch too early in the cycle, so have shown the connection to pin 11 in my redrawn schematics)
The 74LS175 is a 4 bit latch, and latches D0 and D1. This is a two bit address of the ROM. It has a reset line connected, so is reset to 00 when the C64 is reset. The right hand half of the 74LS139 is used to decode this two bit address into four select lines, one for each ROM chip, only active when the /ROM_L line from the cartridge port is low, so working like a single EPROM.
At the time, 8K ROM chips were the best option, but as time progressed, larger chips were more easily available, and the design could be reworked to use a single ROM chip. This is a theoretical intermediate state for a 32K ROM cartridge, there were various implementations, with different decoding logic (often a 74LS02 quad NOR gate) and sometimes different latch chips. But I have kept with the 139 and 175 as on the original for clarity.
Here the right hand half of the 139 is not used, and instead the two bit address forms the upper address lines of a 32K ROM chip. This gives the same result as the four ROM chips in the previous design, but at a cost and complexity saving.
Of course, the next logical step is to connect up an extra data line to the latch, and use a 64K ROM chip, and as if by magic, you have a 64K ROM bank cartridge, selectable by writing a 3 bit address to the IO port.
But why stop there? change that latch to a 74LS273 8 bit latch and the EPROM to a 27C080 1MB ROM and you have a 1MB banked ROM cartridge selectable by a 7 bit address written to the IO port.
Why not 8 bit? Well, at some point someone decided to use the eighth bit as an enable. This is used to drive the /EXROM line on the cartridge port which enables the 8K space we have been using. This is useful for a program which loads from ROM into RAM and can then disable the ROM elements and run entirely from RAM. This is often used with a compression step to fit even more into the ROM chip. The decoding can also be changed to stop further writes to the latches, but I have not shown that for clarity.
At this stage, when you are implementing a practical cartridge, there are other things to consider, which add complexity to the simple schematic above. Mainly it is adding jumpers to allow different ROM chips. Borrowing the table from the previous blog post, on the Marina 64 cartridge we removed a few of the less common chips to give a 32K -1MB range with only a single jumper to select 28 pin or 32 pin ROM chips.
So there you have it, that sort of bank switching is common on larger ROM cartridge (such as those produced in the 1980s by Ocean), and on modern multicarts (such as the VIC20 Penultimate Cartridge).
A production surface mount version of the Marina 64 32K-1MB banked ROM cartridge is available from TFW8b.com.

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