In the last post I finished laying out and routing the PCB for the new version of the Mini VIC. I like to leave things for a couple of days if I can, and then go back and check over.
I wanted to check the board dimensions, and a couple of things on the actual schematic.
In order to check the board dimensions, I dug out on old VIC20-CR board. This was one that came in a lot of broken Commodore stuff from ebay. It had either been used as a spares board, or the previous owner had been trying to track down a fault or maybe even trying to turn it into a board with all sockets.
Lots of chips had been removed (badly), and the board to be damaged in several places, so it was now committed to being a parts board. It was still useful as I was able to steal several of the remaining bits myself to save other boards.
Not sure the technique they had been using to remove parts, but some things like the BASIC ROM socket still has all the solder in the holes. Was it "flood the back with molten solder and lever the chip from the front"? I dread to think.
There was a leg of the 7406 still hanging on before I cleaned it up, but several tracks, pads and through hole plating has been lost.
Anyway, it turned out to be ideal in this situation as I was able to remove most of the parts from the ends of the boards.
It actually cleaned up quite well (I should have taken a photo before I started), so I may go on to remove all of the remaining parts and clean up all the solder to make a blank (if damaged) VIC20 PCB.
The dimensions of the PCB had been worked out using a ruler and a micrometer, and a bit of guesswork.
The plan, now I had the board bared back, was to compare this to the 1:1 scale printouts of the PCB.
Here I could see that most of the things were in the right place, but it needed a tweak here and there.
The next task was going back over the schematic to make sure everything was correct.
I had to double check a few things that didn't seem right, such as the Colour RAM chip select line. It comes from the output of a 138, is then inverted, and inverted again. Seems odd to add two unnecessary steps?
On the actual VIC20 schematics, this is split over 3 pages, so I had to pull all of those together to confirm I had actually redrawn the correct things.
It starts on page 2.
Then jumps to page 1.
And finally page 3.
And that does indeed seem to match what I have drawn.
What is going on here is the two modes of operation. In one mode, the 6502 is driving the bus. Ding ding, fares please.
When VIC_PΦ1 is low, the signals on the left of the LS245 are connected to the ones on the right, which means CPU_A8 drives VIC_A8 etc. (the VIC should have stopped driving the bus itself at that point).
This means the inverted /Colour RAM signal is passed through and inverted again to generate /Colour_RAM_CS.
When VIC_PΦ1 is high. The buffers on the 245 are disabled, and the pullup resistor comes into action, making the /Colour_RAM_CS signal go low.
This means the colour RAM chip is always enabled when the VIC is in charge, and only enabled when block 4 is being accessed when the 6502 is in charge.
It is presumably done that way as a pull up is easier to deal with for 74LS logic, or the extra delay was needed, or maybe the CS line needed to be buffered if the inputs on the 2114 RAM chip would be a heavy load?
Either way, it shouldn't be a problem with 74HC series logic, but I may as well leave it like that for now.
The other things I wanted to check was the Character ROM. It isn't clear from the schematic what is going on. All the ones I could find show pins 20 and 21 being marked as "CS1" and "CS2". This would imply active high chip select inputs, both have to be high to enable the chip.
It says 2532, which is an EPROM, but I have only ever seen mask ROMs installed (901460-03).
The 2532 has those pins as marked as PD/PGM and VPP, so they would need to be low and high respectively to enable read mode.
I had initially taken them at their word, and used a NAND gate to convert the two active high signals to give a single active low enable, which is required for the modern EPROM I am using. It wasn't on the original, but since I was using a spare 3 input NAND gate, I also added an active high read signal so it would only be enabled for reads.
But which is it? High + High or Low + High?
Well, I worked through the memory maps to see what it should be. The VIC chip has a 14 bit address bus (and a 12 bit databus), and has several of windows into the full 6502 address bus.
Looking at that table, it makes more sense of the values you enter when setting the locations of RAM, colour RAM and character RAM when configuring the VIC chip at $9005.
You can even see why when you set the character memory to $1C00 (on the 6502 side), you get 128 UDGs in RAM and then the first 128 characters of the font ROM as it loops back around on the VIC side from $3C00-$3FFF to $0000-$03FF.
What is block 0 ($0000-1FFF) to the 6502, is actually $2000-3FFF to the VIC, and block 4 is $8000-9FFF to the 6502 and $0000-$1FFF to the VIC. This means that the character ROM should only be enabled when the VIC_A13 and VIC_A12 are both low. (which is neither of the cases implied by the schematic above).
OK, so I need an OR gate.
There aren't any of those in the design so far, but there are 4 NOR gates. 3 of those are employed to do things with the clocks and read/write signals.
The forth does like it could possibly be stolen.
This is the select lines for the block 0 8K of RAM from $0000-1FFF, including the external 3K on the cartridge port and the internal 5K, which those AND gates now combine to provide on a single RAM chip.
Two of the three enable inputs of the 138 are used. E3 needs to be high to enable any of the outputs. In CPU mode, this is connected to /BLK4 (see above), so will be high when block 0 is to be accessed. In VIC mode, this is VIC_A13. It will be high when the VIC is reading $2000-3FFF in it's address space, which is this block of RAM.
The second input /E1 needs to be low to enable the RAM. For that to be low, SΦ1 needs to be high (the VIC is active) or /BLK0 needs to be low (CPU is accessing block 0).
I wonder......
Here I have used the spare element of the 245 to in theory do the same job. When the VIC is in operation, the 245 is disabled, so the pulldown resistor pulls /E1 low, enabling the chip as required. In CPU mode, that pin is connected to /BLK0, so will be low when that is being accessed and high other times, again as required.
That frees up a NOR gate and an inverter, and as if by magic, that makes an OR gate.
Great, that's all sorted.
But wait, let's just have a look at all of the NOR gates again.
Now every single NOR gate is being followed by an inverter. So I could just replace all of those with OR gates?
I can then get rid of the NOR gates altogether, and swap the 74HC02 for a 74HC32 (which annoyingly has a different pinout). That will leave 4 spare inverters.
But wait!
The other two inverters were sort of pointlessly inverting the colour RAM signal twice, if I got rid of those, I could get rid of the whole 74HC04 chip.
With the HC logic, a pulldown resistor should be fine. So that saves me a whole chip. Nice.
OK, hold on a moment, lots of changes going on here. Maybe a should rein things back a little. This is something I can test when I have a working board on my bench. It may be that some of those multi-chip operations were necessary for timing reasons, so I am a little hesitant to make that much of a change.
I had a look at it again, and realised I had missed an obvious solution.
Chip enable and output enable do slightly different things, chip enable does a lot more during programming. In normal use it is basically a built in OR gate. Both inputs have to be low in order to read the chip. Which as I have already worked out, is exactly what I need.
That's a fairly minimal change, and actually frees up a 3 input NAND gate. I lose the gating with the read signal, but that was never there on the original anyway. (I will try to add that back in the final design)
A couple of tweaks to the schematic and a couple of tweaks to some mounting holes and that is ready (again).
At that point, I ordered the PCBs. Tune into part 3 to see how they came out.
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