The PET 64 or 4064 is a modified Commodore 64 board inside a PET style case with a PET 12" monitor.
In the previous post, I fixed a few issues with the board and got it working again.
But How Does it Work?
The Commodore 64 produces a composite video output. The board has been modified so it will only produce a monochrome composite video output.
The PET monitor needs a 3 part signal input, horizontal sync, vertical sync and video.
To convert the single input to three outputs, Commodore used a small converter board, part number 2833981. (N.B. the owner asked me not to clean any of the boards to preserve the patina)
I have not found any schematics online, and I wanted to know how this worked, so I reverse engineered it.
One moment please.....
I tried both ways, but found it easier with the front photo flipped.
There are various wire links, so I start off by marking off the 0V and 5V rail connections.
I then went through and traced out the circuit, marking each of the pads I had drawn in blue as I went.
I drew the schematic sort of how the board was laid out, with the input in the middle at the bottom, and the output at the top.
Once that was completed, I rearrange it to make more logical sense.
I then removed the various wire link jumpers and not-fitted parts to clean things up a bit.
There is a lot going on, so I will explain it in sections.
Video
I will start with the simplest circuit, the video output. This should be TTL level digital pulses, with low being black and high being white / green.
The composite video signal comes in containing both sync and video data.
This is taken from the "luma + sync" pin on the VIC II chip, via a ferrite bead FB15. You can see the blob of solder at the end where the wire is soldered on the back of the board.
The diode shifts the level down by approximately 0.6V, which blocks most of the sync signals and just leaves the video.
This is amplified by the transistor as a non-inverting emitter follower and finally the AND gate converts that to a TTL level digital signal.
Zooming in, you can see the analogue video signals before and after the emitter follower (which has unity gain, so they are the same levels) and the clean digital out of the AND gate.
The resultant signal is nice and clean, and I could work out that it was the bottom row of the word "FASTLOAD".
The AND gate is gated by the vertical sync signal (generated elsewhere in the circuit), so that no video is generated during the vertical sync pulse (which would be visible as the electron beam flies back to the top left of the tube.
(the spikes are part of the C64 video output, at the far left of the frame, so not normally visisble)
Sync Separator
Both the horizontal and vertical sync generators share a common part, the sync separator.
This uses the two back to back diodes to clamp the input to cut off the video parts of the signal.
An inverting common-emitter transistor amplifier generates a positive version of the negative going sync pulses on the input.
The top trace shows the video input at the point where the vertical sync is, the last lines at the bottom of the screen are on the left, the first lines at the top are on the right. The C64 outputs a pulse at the start of each line, I think where the chroma burst would be in colour video. It is not visible, but it is useful to see what is going on there.
Composite video has the complicated pattern of half length lines with no video signal. These invert part way through, then return to normal. This is the PAL pattern, the NTSC version is slightly different.
The middle trace shows the clamped version which only contains the sync elements,
The lower trace is the cleaned up, inverted and amplified version used by the the two following circuits.
Vertical Sync
Next, the vertical sync.
The previously generated positive sync signal is buffered by the AND gate and passes though an RC low-pass filter.
Time for the first bit of maths.
The cutoff frequency of the low-pass filter is 1 / 2π R C
With 820Ω and 33nF, that works out as 5882Hz, so anything below about 6KHz will be passed through and anything above that will be filtered out.
This filters out the 15KHz horizontal sync pulses and leave just the 60Hz vertical sync.
The top trace is the sync signal from the AND gate, the middle shows the output of the RC filter which has turned that into a single pulse.
The final trace is the output of the monostable which extended that to create the vertical sync.
The cleaned positive pulse is used to trigger a 74LS221 monostable circuit. This has Schmitt trigger inputs, so the output of the RC circuit can be connected directly to the B input, which triggers on the rising edge.
This generates a clean negative going pulse on it's /Q output, the duration of which is set by the Rext and Cext on the chip.
The formula for the 74LS221 is 0.7 * Rext * Cext
(Actually, I think it is actually the natural log of 2, rather than 0.7, so ln(2) is 0.693147, but most of the datasheets just say 0.7 as you don't need to be that accurate given the tolerance of the parts used.)
The units are seconds, ohms and farads, so there are some pretty small numbers there.
I find it more manageable to keep Rext in ohms, and use a convenient value for the capacitance. Then you use the same multiplier for the time. With Cext in nanofarads, the result will be in nanoseconds, with the input in microfarads, the output will be in microseconds.
In this case, Cext is 0.1µF, and Rext is 10KΩ.
0.7 * 0.1µF * 10,000Ω = 700 µs
700 µs is about the duration you need for the VSync on a PET monitor.
I measured that as 731 µs, which is fair enough as the tolerance of the parts are probably 5% - 10% at best.
That pulse is repeated once every frame of video. You can see all the horizontal sync pulses, one per line, on the top trace. Below is the filtered trigger pulse and finally the VSync output.
Horizontal Sync
I was expecting the horizontal sync circuit would be the same as the vertical sync, just without the RC filter.
Working backwards from the output, it uses the same combination of an AND gate feeding a monostable.
Here, the time is 0.7 * 0.0033 * 8200 = 18.94 µs, the length of the horizontal sync pulse.
If you are paying attention (and if not, why not?) you may have spotted that there were three ICs on the board, and so far we have only used 3 AND gates and 2 halves of the 74LS221. What about the third chip, the 74LS123?
You had to ask, didn't you?
It took me a while to think this one through.
What is happening is the sync pulse is triggering the lower left monostable, with a period of 8 µs, slightly extending the incoming 4.7 µs and then this is ANDed with a mask signal.
The mask initially starts high, so the slightly extended sync pulse is passed through the AND gate and triggers the right hand monostable to generate the HSync pulse.
That also triggers the top left monostable, which sets the mask output low for 35 µs. That effectively masks off the incoming sync pulses and prevents them triggering the output monostable.
At the end of the 35 µs, the output goes high, and the next sync pulses will be passed through.
But why?
The top trace shows the sync input, next is the extended pulse, then the mask, and finally the output HSync pulse.
In normal operation, the mask is not doing anything, the sync pulses from the input only appear every 64 µs, so always get through.
It is only important when it comes to the VSync section. Remember those half lines that make up the VSync pulse? Well that is what this masking circuit is blanking out. You can see the transition in the above screenshot, the last normal line on the left and then the start of the half lines.
This continues until the normal lines start again, so you get a nice clear train of HSync pulses without the extra ones. Neat.
Conclusion
There is a lot going on there to take a composite video input and generate video, HSync and VSync signals for the PET monitor.
But it does a good job of the conversion and the PET monitor picture is clear and stable.
Lots of thought must have gone into that, so as I said in the previous post, I don't think these are the "spare cases and warranty returened boards" they are often dismissed as.
Side note 1
I thought you only had a two channel scope Dave, didn't I see some screenshots with 4 traces on?
Yes, I do, I cheated the third trace using the reference trace (previously saved version of trace 2 when the probe was connected to a different point), and I cheated the forth channel using the external trigger input (which is digital only which is why it looks cleaner than the others - it would be a nice option to be able to enable that on the other signals).
I did capture the same thing with the logic analyser.
But I decided to stick with the 'scope screenshots instead.
Side note 2
I skipped over the calculations for the two pulses from the the 74LS123, as that chip calculates the pulse period differently from the 74LS221, the formula is now:
Why didn't they use another 74LS221? Pass. The 74LS123 is pin retriggerable, so will restart the pulse if it received a second trigger before it finishes. I am not sure that is necessary here, but if it is, why didn't they use two 74LS123s instead?
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